Deep Learning Compiler Optimization Systematic Literature Dossier

Role: Staff AI Systems Research Engineer specializing in deep learning compilation, intermediate representations, and tensor runtime optimization.

Context

• Workload architecture family: {{model_architecture_family}}
• Target hardware execution backends: {{target_hardware_backends}}
• Research literature corpus: {{source_paper_corpus}}
• Core optimization primitives: {{optimization_primitives}}
• Memory bandwidth and compute limits: {{memory_bandwidth_limits}}
• Framework integration target: {{framework_integration_target}}

Task

Author a comprehensive academic literature review report that analyzes compiler techniques across {{source_paper_corpus}}, assessing automated fusion, layout transformation, and code generation strategies for {{model_architecture_family}} executing on {{target_hardware_backends}}.

Method

1. Review the intermediate representation (IR) designs in {{source_paper_corpus}}, comparing multi-level IRs (e.g., MLIR dialects) against single-level tensor graph representations.
2. Trace graph-level optimizations, evaluating operator fusion heuristics, constant folding, and dead code elimination techniques.
3. Analyze loop transformation and polyhedral optimization strategies detailed in the papers for tensor contraction workloads.
4. Examine auto-tuning algorithms (e.g., cost models, reinforcement learning, genetic search) for tiling and layout selection under {{memory_bandwidth_limits}}.
5. Evaluate hardware-specific codegen approaches targeting compute units and scratchpad memory within {{target_hardware_backends}}.
6. Compare quantization-aware compilation and mixed-precision lowering mechanisms reported in the literature.
7. Assess engineering integration complexity for {{framework_integration_target}}, pinpointing missing compiler passes or execution runtime overheads.
8. Formulate a comparative taxonomy of compiler frameworks based on compilation latency, peak memory utilization, and inference speedup.

Constraints

• MUST provide mathematical and algorithmic descriptions of optimization passes discussed in {{source_paper_corpus}}.
• MUST evaluate memory footprint implications (SRAM/HBM) specifically for {{memory_bandwidth_limits}}.
• MUST NOT rely on marketing benchmarks; critique published baseline fairness and hardware configurations.
• Keep all analyses grounded in system-level concepts such as instruction cache pressure, memory coalescing, and PCIe/NVLink overheads.

Output format

Deliver an advanced technical literature review containing:

1. Executive Summary & State-of-the-Art Landscape (max 300 words)
2. IR Design & Graph Rewriting Comparative Analysis
3. Kernel Generation & Polyhedral Transformation Audit
4. Hardware Mapping & Memory Subsystem Efficiency Assessment (structured table)
5. Gap Analysis & Production Adoption Strategy for {{framework_integration_target}}

Self-review

• Confirm that every technique in {{optimization_primitives}} is explicitly assessed against {{source_paper_corpus}}.
• Ensure compute and memory trade-offs reflect the specific hardware architecture of {{target_hardware_backends}}.
• Verify that compiler pass limitations are clearly distinguished from theoretical framework capabilities.