Deep Learning Architecture Feasibility Specification

Role: Principal Research Scientist in Machine Learning Systems

Context

• Target model capability: {{target_capability}}
• Current baseline architecture: {{baseline_architecture}}
• Latency and memory budget: {{latency_memory_constraints}}
• Academic literature corpus: {{academic_corpus_scope}}
• Workload and input profile: {{target_workload_characteristics}}
• Production hardware profile: {{hardware_target}}

Task

Produce an exhaustive algorithmic architecture specification based on a systematic review of {{academic_corpus_scope}}, evaluating state-of-the-art methods against {{baseline_architecture}} to establish a mathematically sound, hardware-viable reference architecture for {{target_capability}}.

Method

1. Extract and classify algorithmic paradigms across {{academic_corpus_scope}} addressing {{target_capability}}.
2. Normalize theoretical FLOP counts, parameter scaling laws, and memory access patterns reported in literature for {{hardware_target}}.
3. Compare empirical convergence rates, inductive biases, and stability traits against {{baseline_architecture}} under {{target_workload_characteristics}}.
4. Map identified attention, recurrence, or state-space mechanisms against {{latency_memory_constraints}}.
5. Reconcile conflicting academic benchmark claims by isolating differences in dataset normalization and evaluation harness setups.
6. Formulate a unified mathematical definition of the selected optimal architecture.
7. Detail tensor shape invariants, compute graph topology, and attention/routing layer implementations.
8. Specify empirical validation protocols and ablation test suites to verify academic claims in production.

Constraints

• MUST express all neural operators and layer transformations using rigorous mathematical notation.
• MUST NOT recommend architectures whose theoretical peak memory exceeds {{latency_memory_constraints}} on {{hardware_target}}.
• Spec MUST explicitly distinguish peer-reviewed findings from unverified pre-print empirical claims.
• All performance claims must reference theoretical bounds established in {{academic_corpus_scope}}.

Output format

Deliver a formal technical specification structured into:

1. Literature Synthesis & Theoretical Taxonomy (max 300 words)
2. Architectural Trade-off Matrix (Markdown table comparing 4-5 mechanisms across 6 quantitative dimensions)
3. Formal Architecture Specification (layer-by-layer mathematical definitions, tensor dimensions, pseudocode)
4. Hardware Roofline & Bottleneck Analysis for {{hardware_target}}
5. Validation & Ablation Protocol (numbered sequence of test criteria)

Self-review

• Verify every mathematical symbol is defined and consistent across equations.
• Check that memory footprint calculations strictly adhere to {{latency_memory_constraints}}.
• Ensure baseline comparison explicitly addresses failure modes of {{baseline_architecture}}.