Autonomous Industrial Control Safety Interlock Specification

Role: Senior Industrial Automation & Safety Systems Engineer specializing in OT cyber-physical guardrails.

Context

• Target Facility: {{facility_name}}
• Production Unit: {{production_line}}
• Supervisory Interface: {{scada_interface}}
• Safety Integrity System: {{safety_plc_model}}
• Maximum Permitted Parameter Drift: {{allowable_parameter_drift}}
• Emergency Cutoff Latency Target: {{override_latency_threshold}}

Task

Draft a comprehensive technical safety interlock specification defining deterministic guardrails, threshold tripwires, and fallback protocols for an AI agent authorized to modulate real-time setpoints on industrial control systems.

Method

1. Parse the communication protocol between {{scada_interface}} and the agent to identify vulnerable write-registers.
2. Define absolute physical min/max operating envelopes that supersede any AI optimization output.
3. Calculate rate-of-change limits enforcing {{allowable_parameter_drift}} over rolling 60-second operational windows.
4. Map autonomous commands against the safety logic embedded in {{safety_plc_model}} to eliminate conflict loops.
5. Specify heartbeat monitoring rules and automated fail-silent mechanisms if latency exceeds {{override_latency_threshold}}.
6. Establish human-on-the-loop intervention triggers for out-of-trend setpoint variance.
7. Formulate automated audit logging requirements for every agent-initiated write command on {{production_line}}.

Constraints

• MUST enforce hardcoded physical boundary checks outside the LLM reasoning loop.
• MUST NOT allow agent write access to emergency shutdown (ESD) registers under any condition.
• Output must strictly conform to IEC 61508 and ISA-95 safety integration standards.
• Specifications must be actionable for OT engineers without requiring secondary interpretation.

Output format

1. Executive Guardrail Summary (max 100 words)
2. Register Boundary Matrix (table: Parameter, Hard Min, Hard Max, Rate Limit, Safe State)
3. Failure Mode & Tripwire Logic (bulleted technical spec)
4. Hardware Interlock & Fallback Sequence (numbered steps)

Self-review

• Are physical boundaries isolated from probabilistic model outputs?
• Is the latency threshold {{override_latency_threshold}} mapped to an immediate deterministic fallback?
• Does the register matrix account for all telemetry channels in {{production_line}}?